Automatic and continuous time adjusting device for a clock



Sept. 29, 1970' R. MARTI 3,530,663

AUTOMATIC AND CONTINUOUS TIME ADJUSTING DEVICE FOR A CLOCK Filed May 16, 1968 2 Sheets-Sheet 2 FIG.3

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United States Patent 3,530,663 AUTOMATIC AND CONTINUOUS TIME ADJUSTING DEVICE FOR A CLOCK Raymond Marti, Chatelaine, Geneva, Switzerland, assignor to Patek Philippe S.A., Geneva, Switzerland Filed May 16, 1968, Ser. No. 729,597 Claims priority, application Switzerland, Sept. 1, 1967,

12,290/ 67 Int. Cl. G04c 3/00 U.S. C]. 5823 7 Claims ABSTRACT OF THE DISCLOSURE The invention concerns an automatic and continuous time setting device for an electronic clock in which the correction signals are obtained by the comparison of the oscillating frequency of the clock or a division thereof with broadcasted reference frequency. The clock comprises further means hindering any time setting if the reception of the broadcasted reference frequency is not received correctly.

The present invention has for its object an automatic and continuous time adjusting device for a clock, characterized by the fact that it comprises a receiver tuned on a time signal emitter with seconds modulation delivering a first train of impulses; a comparator comparing this first train of impulses with a second train of impulses supplied by the oscillator of the clock and delivering correction signals if the interval between the first and the second train of impulses exceeds a predetermined value; a correction device fed by these correction signals and modifying the second train of impulses in order to correct the error; and a control device prohibiting any correction if the reception of the receiver is defective.

The attached drawings show schematically and by way of example an embodiment of the device according to the invention.

FIG. '1 is a block diagram of the device of the invention.

FIG. 2 is a detailed diagram of the control device.

FIG. 3 shows the shape of voltage Uc.

The automatic and continuous time adjusting device shown comprises a receiver 1 detecting the impulses transmitted by an emitter with seconds modulation and delivering a first train of impulses which are shaped by a Schmitt-trigger circuit 2 preceded by an integrator 3 preventing the untimely release of the monostable multivibrator 4, whereby all these three parts belong to the comparator I.

A second monostable multivibrator 5 of the comparator is fed by a second train of impulses with a frequency of 1 Hz. derived from the oscillating device 6 of the clock, quartz, tuning fork, etc., by frequency division in 7.

The direct outlet Y of the monostable multivibrator 4 is differentiated in 8, then delayed by some hundredths of a second in 9 before being delivered to a NAND gate 10 in A.

The reverse outlet Y of the monostable multivibrator 4 is delivered in D to a NAND gate 11.

The direct outlet Z of the second monostable multivibrator S is differentiated in 12, then delivered in C to the gate 11..

The reverse outlet 2 of the monostable multivibrator 5 is delivered in B to the gate 10.

The correction signals delivered by the comparator, i.e. by one or the other of the gates 10, 11 feed on the one hand a lagging display 13, or a leading display 14 respectively, and on the other hand the correction device II.

This correction device II is made up of a bistable multi- 3,530,663 Patented Sept. 29, 1970 vibrator 15, fed on the one hand directly by the signal of 1 kHz. of the oscillator 6 or of the preliminary frequency division and on the other hand by the lagging error signal R. The outlet of this bistable multivibrator is combined with the high frequency signal delivered by the oscillator 6 by an AND gate 16.

The outlet of this AND gate 16 feeds one of the inlets of an OR gate 17 the other inlet of which is fed by the leading error signal A, whereas its outlet feeds the inlet of the frequency divider 7.

The automatic time adjusting device comprises also a control device III prohibiting an abusive or untimed correction for example when the signals delivered by the receiver 1 are not satisfactory.

This control device is shown in detail at FIG. 2 and is based on the control of the duration of the impulses as well as of the absences of the signals delivered by the receiver 1.

The signals of the receiver are applied on the base of a transistor 18 which is saturated at the moment of the 0.1 second impulse which causes the discharge of the capacitor C through the resistor R2. When the transistor is blocked, the capacitor C charges again through the resistor R1. If one chooses R1-K R2 (corresponding to the ratio of the signal and silence control), one will have a voltage Uc at the clamps of the capacitor which will slightly oscillate about an average value (see FIG. 3).

It is evident that one can equally conceive the control circuit in such a Way that the capacitor C is charged while the transistor is passing.

This voltage is controlled by an amplifier 19 the zero of which corresponds to the value of equilibium in normal reception. If the reception is disturbed (parasites, disturbing noise, break-down of the emitter etc.), the amplifier 19 will command the switching on of a signal lamp 20 of defective reception and will simultaneously deliver a voltage Us 0 on the NAND correction gates 10 and 11 blocking them and therefore hindering any automatic correction.

The working of the described automatic time adjusting device is the following:

The impulses coming from the receiver and from the clock are transformed into impulses of a duration of 0.5 second.

Those of the receiver are previously shaped by a Schmitt-trigger having an integrator circuit which reduces the risk of an untimely release of the monostable multivibrator.

After derivation, these impulses A and C are applied on a NAND gate which, in normal condition (clock in operation), is closed by the signals B, D (condition 0) coming from the reverse outlet of the other monostable multivibrator.

If for example, the clock is lagging, the impulse A arrives at the moment when the signal B is I; the impulse for commanding the advance together with the signalling of the backlog will be present if the signal X is I.

The signal X 1 means that the quality of the signals received from the receiver is good. In the contrary case, we have the condition 0 and the red signal lamp flashes up to signal the defective reception. In this way, no untimed correction will be executed.

If the clock is in advance, the process is the same.

The delay circuit connected in the impulse A avoids a perpetual oscillation of the corrections by the introduction of a threshold.

In the case of a lag of the clock, the correction impulse comes through the OR circuit directly to be added to the counting of the 1 kHz. of the frequency division. We will therefore have a correction of the condition of +0.001 sec./sec.,

The case of an advance of the clock, the correction impulse causes the swinging of the flip-fiop, point N of which passes over to the condition 0. The following impulse of 1 kHz., arriving at point M, can therefore not pass the AND circuit (M.N.). But simultaneously, this impulse causes the return of the flip-flop which puts point N into condition I with a slight delay, thus permitting the passage of the following impulses M. We have therefore subtracted one impulse from 1 kHz. at the 1 kHz. counting. The condition will be corrected by 0.001 sec/sec. The control device is absolutely necessary if the automatic time adjustment wants to be used with a maximum of security. It guarantees a protection against the absence of an emission, the too weak signals, the ambient parasites and the neighbouring disturbing emitters (interference) and permits to avoid any time adjustment which could take place under bad conditions and so produce errors.

The advantages of a clock with an automatic and continuous time adjustment as described are the following:

the absence of a periodical time adjustment, therefore of a comparison of the condition,

the oscillator which is an expensive element in a precise quartz clock can be replaced by a less precise and cheaperv oscillator (quartz, tuning fork, RC or LC circuits etc.) which can work at frequencies lower than 1 kHz. and with a time adjustment of even lower frequency,

the easy and economical obtaining of the same hour (same condition) at different geographical points without precise clocks or chronographs.

In a variant, the correction device II described hereinbefore could be replaced by adevice which in response to the correction signal allows to modify the frequency of the reference oscillator or of the oscillating device 6 in order to realize the desired correction.

I claim:

1. An automatic and continuous time adjusting device for a clock having an oscillator, comprising a receiver tuned on a time signal emitter with seconds modulation delivering a first train of impulses; a compartor comparing this first train of impulses with a second train of impulses supplied by said oscillator and delivering correction signals if the interval between the first and the second train of impulses exceeds a predetermined value; a correction device fed by these correction signals and modifying the second train of impulses in order to correct the error; and a control device prohibiting any correction if the reception of the receiver is defective.

2. Device according to claim 1, the control device comprising a transistor on the base of which the signals coming from the receiver are applied, a resistor and capacitor network located in the output circuit of said transitor and having a time constant during which said capacitor charges while this transistor is blocked, and an amplifier fed by the voltage at the clamps of the time constant and delivering a signal as soon as this voltage exceeds the predetermined limits.

3. Device according to claim 1, the control device comprising a transistor on the base of which the signals coming from the receiver are applied, a resistor and capacitor network located in the output of said transistor and having a time constant to which said capacitor discharges while this transistor is blocked, and an amplifier fed by the voltage at the clamps of the time constant and delivering a signal as soon as this voltage exceeds the predetermined limits.

4. Device according to claim 2, the comparator comprising two NAND gates each fed by trains of impulses corresponding to said first and second trains of impulses in order to deliver a correction lag and a lead signal when these two trains do not coincide, said NAND gates being also connected to the output of the control device, these circuits being blocked when the control device delivers a signal.

5. Device according to claim 1, the correction device modifying according to the correction signals, the frequency of the second train of impulses.

6. Device according to claim 1, the correction device modifying the phase of the second train of impulses,

7. Device according to claim 3, the comparator comprising two NAND gates each fed by trains of impulses corresponding to said first and second trains of impulses in order to deliver a correction lag and a lead signal when these two trains do not coincide, said NAND gates being also connected to the output of the control device, these circuits being blocked when the control device delivers a signal.

References Cited UNITED STATES PATENTS 3,217,258 11/1965 Arlin et a1. 58-35 RICHARD B. WILKINSON, Primary Examiner E. C. SIMMONS, Assistant Examiner US. Cl, X.R. 

